High layer PCBs (usually referring to PCBs with ≥ 10 layers) are the core basic components in the field of electronic information, widely used in scenarios such as servers, 5G communication equipment, aerospace, and high-end medical instruments. Its processing difficulty far exceeds that of conventional multilayer boards (≤ 8 layers), and the core challenges lie in precise alignment between layers, reliability of inner layer circuits, high thickness to diameter ratio electroplating, and multi process collaborative control. The following analysis is based on six core processes: material selection, inner layer production, lamination process, drilling and electroplating, surface treatment, and testing and verification, combined with professional terminology:

1、 MATERIAL SELECTION: SUITABLE FOR THE BASIC CARRIER WITH HIGH MULTILAYER CHARACTERISTICS

The requirements for material properties of multi-layer PCBs focus on high glass transition temperature (Tg), low coefficient of thermal expansion (CTE), stable dielectric properties (Dk/Df), and voltage resistance. The substrate combination needs to be selected according to the application scenario (such as high frequency, high power, and high reliability).

1. Core board selection

Core board is a multi-layered "skeleton" composed of fiberglass cloth and epoxy resin composite, which must meet the following requirements:

Tg value: FR4 with Tg ≥ 130 ℃ (such as MEGTRON 6) is commonly used for high multi-layer applications, while low Df materials (such as Rogers RO4350B, Df ≤ 0.0037) are required for high-frequency scenarios (such as 5G base stations);

Thickness uniformity: The thickness deviation of the core board should be ≤± 5 μ m (conventional board should be ≤± 10 μ m) to avoid warping after lamination;

Voltage resistance: High voltage scenarios (such as power modules) require the use of corona resistant materials (such as polyimide substrates) with a breakdown voltage of ≥ 3kV.

2. Selection of Prepreg (PP)

PP sheet is a key medium for interlayer bonding, composed of uncured epoxy resin and fiberglass cloth. Its parameters directly affect interlayer bonding and medium thickness:

Model matching: 7628 (thick resin, suitable for large spacing layers), 2116 (thin resin, suitable for fine circuits) or 1080 (ultra-thin, used for HDI high multilayer) are commonly used for high multilayer;

Resin Content (RC): It needs to be matched with the thickness of the core board (for example, when the core board thickness is 0.1mm, the RC of PP is usually 45% -55%), to avoid insufficient thickness of the medium or overflow after compression;

Pre solidification degree (Flow): High and multi-layer layers require low flow PP (Flow ≤ 30%) to prevent interlayer misalignment caused by resin flow during compression ("flow glue").

2、 INNER LAYER PRODUCTION: THE CORNERSTONE OF HIGH MULTI-LAYER PRECISION AND RELIABILITY

The inner layer is the core structural layer of multiple layers (usually even layers, such as 4/6/8 core boards), and its manufacturing accuracy directly determines the registration quality between the layers of the entire board. The key processes include pattern transfer, oxidation treatment, and inner layer etching.

1. Inner layer graphic transfer

Convert the design file (Gerber) into an inner layer circuit pattern using negative film technology (conventional) or positive film technology (fine circuit):

Coating photosensitive adhesive: dry film (DF) or wet film (Wet Film), the dry film thickness is usually 25 μ m (17 μ m for fine circuits), and the film temperature (110-130 ℃) and pressure (0.3-0.5MPa) need to be controlled to avoid bubbles;

Exposure and development: LDI (laser direct imaging) is used instead of traditional film, with a resolution of up to 20 μ m (line width/line spacing ≤ 100 μ m), and the exposure energy needs to be adjusted according to the dry film thickness (such as 80-100mJ/cm ² for 25 μ m dry film energy);

Key parameters: The inner layer line width tolerance should be controlled within ± 10% (conventional board ± 15%), and the line spacing should be ≥ 3 times the line width (to avoid short circuits caused by side corrosion).

2. Inner layer oxidation treatment

Enhance the adhesion between the copper surface of the core board and the PP sheet, commonly using Black Oxidation or Brown Oxidation:

Blacking: By oxidation with NaOH+KMnO ₄ solution, a CuO/Cu ₂ O mixed layer (thickness 0.5-1 μ m) is formed on the copper surface, with a surface roughness Ra of 0.8-1.2 μ m, suitable for high Tg materials;

Browning: Use H ₂ SO ₄+K ₄ [Fe (CN) ₆] solution to generate Cu ₂ O nanowires (thickness 0.3-0.5 μ m) with Ra=0.5-0.8 μ m, which is more environmentally friendly and has better compatibility with low CTE materials.

3. Inner layer etching

To remove the unexposed copper layer and form an inner layer circuit, it is necessary to control:

Etch Factor: Line width/side etching amount ≥ 3:1 (conventional board 2:1), to avoid thinning of the circuit (side etching rate ≤ 15%);

Micro etching control: After etching, micro etching (sodium persulfate+sulfuric acid) is required to remove the oxide layer and roughen the copper surface (Ra=0.3-0.5 μ m) to prepare for the transfer of the outer layer pattern.

3、 STACKING PROCESS: THE "BONDING ART" OF MULTI-LAYER CASCADING

Layering is the process of alternately stacking inner core boards and PP sheets, and forming an overall structure through high-temperature and high-pressure curing. High layer (such as 16 layers) need to be laminated multiple times (such as "2+2 → 4+4 → 8+8"), and the core difficulty is the alignment accuracy between layers and the uniformity of medium thickness.

1. Stack Up design must meet the following requirements:

Symmetry: The core board and PP sheet should be symmetrically distributed (such as the same material for the first and 16th layers) to avoid warping after compression;

Dielectric thickness matching: Total dielectric thickness=∑ PP thickness+core plate thickness, calculated according to impedance requirements (such as controlling dielectric thickness ± 5% for 50 Ω differential lines);

Process edge and positioning hole: Reserve 5-10mm process edge (including positioning hole and Mark point) at the edge, with a hole diameter tolerance of ± 0.05mm (to ensure alignment of each layer during compression).

2. Control of compression parameters

Temperature: The curing temperature of epoxy resin is usually 170-180 ℃ (phenolic resin 150-160 ℃), with a heating rate of ≤ 5 ℃/min (to avoid premature flow of PP sheets);

Pressure: Initial pressure 0.5-1MPa (discharge air), peak pressure 3-5MPa (ensure adhesion), holding time 60-120 minutes (resin fully cured);

Vacuum degree: Vacuum ≤ -0.09MPa (to prevent residual bubbles, high multi-layer vacuum degree requirements are 20% higher than conventional plates).

3. Inter layer alignment (Registration)

Using a laser alignment system (such as Orbotech's Laser Alignment), measure the offset of each layer's Mark points (usually 4 points/layer), with a tolerance of ≤± 25 μ m (HDI multi-layer ≤± 15 μ m). If the tolerance is exceeded, the stacking sequence needs to be readjusted.

4、DRILLING AND ELECTROPLATING: THE 'ELECTRICAL BRIDGE' THAT CROSSES LAYERS

The drilling and electroplating of multiple layers need to address the challenges of high aspect ratio (AR=hole depth/diameter) and multi-core board stacking. Key processes include mechanical drilling, laser blind holes, full plate electroplating (PTH), and pattern electroplating.

1. Drilling process

Mechanical drilling: used for through holes, with a diameter of ≥ 0.2mm (≤ 0.1mm requires laser drilling), and needs to be controlled:

Drill bit material: hard alloy (WC Co) or coated drill bit (TiN/TiAlN) to enhance wear resistance;

Drilling parameters: rotation speed S=100000-20000rpm (small aperture), feed rate F=0.01-0.03mm/r (to avoid tool breakage);

Hole wall quality: roughness Ra ≤ 3 μ m (conventional plate Ra ≤ 5 μ m), to avoid "voids" after electroplating.

Laser Via: Used for HDI multilayer (such as blind buried holes with more than 10 layers), using UV laser (wavelength 355nm) or CO ₂ laser (wavelength 10.6 μ m), aperture 0.05-0.2mm, to be controlled:

Heat affected zone (HAZ): ≤ 50 μ m (to avoid burning the inner circuit);

Hole type: taper ≥ 10 ° (ensuring electroplating filling effect).

2. Full plate electroplating (PTH)

Deposition of thin copper (approximately 0.5-1 μ m) on the hole wall to make the insulating hole wall conductive requires addressing the issue of uneven electroplating caused by the thickness to diameter ratio in high multilayer coatings

Current density: 1.5-3A/dm ² (conventional board 1-2A/dm ²), high thickness to diameter ratio (AR ≥ 10:1) needs to be increased to 3-5A/dm ²;

Additives: Use leveling agents (such as polyethylene glycol PEG), accelerators (such as chloride ions Cl ⁻), and inhibitors (such as thiourea) to inhibit the "Dog Bone" effect (pore copper thickness>pore center);

Thickness control: The thickness of the hole copper should be ≥ 0.8mil (1mil=25.4 μ m), and the thickness of the surface copper should be ≥ 1mil (according to IPC-6012 standard, the thickness of the high multi-layer should be ≥ 1.5mil).

3. Graphic electroplating

Thicken copper plating on the copper surface where the outer layer of the circuit has been etched (to the target thickness, such as plating to 3oz for 2oz substrate), and then tin plating to protect the circuit:

Anode selection: For high current density, titanium baskets are used to pack phosphor copper balls (purity ≥ 99.9%), while for low current density, soluble anodes (copper plates) are used;

Thickness uniformity: The deviation of copper thickness for the entire board is ≤± 5% (for conventional boards it is ≤± 10%), and regular measurements (such as X-ray thickness gauges) are required;

Tin layer thickness: 8-12 μ m (to protect the circuit and prevent excessive etching).

5、 SURFACE TREATMENT: THE 'LAST STEP' IN IMPROVING WELDABILITY AND PROTECTION

The surface treatment of multi-layer materials needs to consider requirements such as solderability, yellowing resistance, and fingerprint resistance. Common processes include chemical nickel gold (ENIG), immersion silver (Immersion Ag), and OSP (Organic Solderability Protector). Among them, ENIG is most suitable for multi-layer precision components (such as BGA and QFP) due to its high flatness (Ra ≤ 0.05 μ m).

1. Chemical nickel gold deposition (ENIG)

Nickel layer: thickness 3-5 μ m (to prevent copper from diffusing into the gold layer), pH value (4.5-5.5) and temperature (80-85 ℃) need to be controlled to avoid "black pad" (caused by abnormal phosphorus content in the nickel layer);

Gold layer: thickness 0.05-0.1 μ m (only needs to cover the surface of the nickel layer), ultra thick gold (>0.15 μ m) can cause welding brittleness;

Cost: accounting for 15% -25% of the total cost of the high tier (with significant fluctuations in gold prices).

2. OSP (Organic Solderability Protective Agent)

Principle: Form an organic film (such as benzimidazole derivatives) on the copper surface, with a thickness of 0.2-0.5 μ m, to protect the copper surface from oxidation;

Advantages: Low cost (1-3 yuan/㎡), smooth surface (suitable for fine pins);

Limitations: Short protection period (only 1-3 months), strict control of storage environment is required (humidity ≤ 40%, temperature ≤ 25 ℃).

6、 TESTING AND VERIFICATION: THE 'LAST LINE OF DEFENSE' TO ENSURE HIGH LAYER RELIABILITY

High level layers require multi-dimensional testing to verify performance, with key items including interlayer alignment, electrical performance, mechanical strength, and reliability.

1. Inter layer alignment check (Registration Check)

Tool: X-Ray drilling machine (such as Hitachi X-6000), measure the offset of Mark points in each layer;

Standard: Inner alignment tolerance is ≤± 25 μ m, outer alignment is ≤± 15 μ m (HDI multilayer is ≤± 10 μ m).

2. Electrical performance testing

Impedance testing: Use TDR (Time Domain Reflectometer) to measure the impedance of differential/single ended wires (such as 50 Ω± 5%, 100 Ω± 5%);

Voltage withstand test: According to IPC-TM-650 standard, apply 1.5 times the rated voltage (such as testing 150V on a 100V board) for 1 minute without breakdown.

3. Mechanical performance testing

Board warping detection: Use a board warping tester (such as IPC-6012 standard), with a warping degree of ≤ 0.5% (conventional board ≤ 1.0%);

Thermal shock test: 500 cycles at -40 ℃~125 ℃ without delamination/cracking (high Tg materials need to pass 1000 cycles).

4. Reliability testing

Cold and hot cycles: -55 ℃~125 ℃ for 1000 cycles, with no breakage in the circuit;

Damp heat aging: After being placed in an environment of 85 ℃/85% RH for 1000 hours, the insulation resistance is ≥ 100M Ω (conventional board ≥ 50M Ω)

SUMMARY: THE CORE LOGIC OF HIGH LAYER PCB PROCESSING

The processing of multi-layer PCBs is a systematic engineering of materials, processes, equipment, and testing. The key lies in controlling interlayer bonding through precision lamination, ensuring electrical connectivity through high thickness to diameter ratio electroplating, and improving alignment accuracy through laser/VDI alignment, ultimately achieving the performance goals of "high reliability, high integration, and high stability". With the development of technologies such as 5G/6G and AI servers, high multi-layer PCBs are evolving towards higher layers (≥ 20 layers), finer lines (≤ 50 μ m), and lower Df (≤ 0.002), promoting continuous innovation in processing technology.